Center for Materials, Devices and Integrated Systems Seminar
September 24 (Friday), 2021: 12:00 pm – 1:00 pm (EDT)
“Selective and Atomic Scale Processes to Enable Future Nano-Manufacturing”
by: Dr. Robert D. Clark
Technical Director, TEL Technology Center, America, LLC
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Abstract: Moore’s law has driven scaling of semiconductor devices to the point that modern feature sizes can be measured in atomic dimensions.(1,2) As shrinking the device footprint becomes increasingly difficult a new power, performance, area and cost scaling paradigm making use of vertical scaling has emerged; initially by adopting non-planar devices, and now by stacking devices on top of one another to create 3D architectures as well.(3) Fabricating 3-dimensional electronic structures with atomic scale dimensions in high yields presents a number of daunting process challenges. Among these are the need to tightly control film thickness, uniformity, morphology, and composition within high aspect ratios. The need for selective deposition of both functional films and sacrificial layers presents another challenge if we are to transition towards a more additive style of nano-manufacturing. Selective and atomic scale processes are being developed in order to enable a number of self-aligned process schemes as well as scaling boosters required for future device nodes.(4) Dielectric on dielectric (DoD) selective deposition is being developed to enable fully self-aligned vias, alleviating edge placement error challenges encountered when manufacturing advanced interconnects. Selective metal on metal (MoM) depositions are useful for depositing metal capping layers as well as hardmasks. Scaling boosters such as air gaps, super-vias and buried power rails could benefit from well-controlled processes with topographical selectivity. And dielectric on metal depositions (DoM) could provide relief from the growing overburdens needed to enable chemical mechanical planarization during replacement metal gate integration in the front end. Progress in these areas as well as future needs and an outlook on future device scaling pathways will be presented.
1. (a) Moore, G. E., Electronics 1965, 38 (8); (b) Bohr, M., Technical Digest of the IEEE International Electron Devices Meeting, Washington, D.C., 2011; pp 1-6.
2. Clark, R.D., Materials 2014, 7 (4), 2913-2944.
3. Clark, R., Tapily, K., Yu, K.-H., Hakamata, T., Consiglio, S., O’Meara, D., Wajda, C., Smith, J., Leusink, G. APL Materials 2018, 6, 050283.
4. Parsons, G.N. and Clark R.D. Chem. Mater. 2020, 32, 12, 4920–4953
Biography: Robert D. Clark, Ph.D. joined Tokyo Electron (TEL) in 2006 at TEL Technology Center, America, LLC (TTCA) in Albany, NY. In 2010 he relocated to Silicon Valley and is currently a Sr. Member of the Technical Staff. His research focuses on thin film process technologies for advanced and emerging devices, materials, and interconnect structures for use in semiconductor manufacturing. Dr. Clark has contributed to processes for advanced CMOS contacts and high k and metal gate structures used currently in advanced semiconductor device manufacturing.
Prior to joining Tokyo Electron, Dr. Clark was a Principal Research Chemist for Air Products and Chemicals, Inc. (APCI) where was the lead technologist for the development of high k and metal gate precursors and helped to develop the first precursor used for ALD high k gate dielectrics in CMOS manufacturing. Dr. Clark completed his Ph.D. in Chemistry at the University of California, Irvine in 2000 and B.S. and M.S. degrees in Chemistry at Virginia Polytechnic Institute and State University (Virginia Tech), Blacksburg, VA, USA in 1993 and 1995 respectively.
Dr. Clark has served previously as the science advisory committee chair for SRC device sciences, and has received the SRC Mahboob Khan outstanding industrial liaison award. He currently contributes to SRC Decadal Plan executive committee, and is a member of multiple conference committees including the AVS ALD, AVS ASD, and VLSI-TSA conference committees. At TEL he has been a U.S. employee of the year, and in 2018 received the most impactful patent award for the U.S. as well. He currently holds more than 60 issued U.S. patents and has authored or co-authored hundreds of journal and conference publications including numerous invited/plenary talks and articles.